1. Field of the Invention
The present invention relates to a memory device, and more particularly, to an EPROM writing circuit in which a voltage level to be applied to an EPROM in EPROM writing is varied and applied to a bit line of a EPROM cell.
2. Description of the Background Art
FIG. 1 is a circuit diagram showing a construction of a general EPROM writing circuit in accordance with a conventional art.
As shown in the drawing, the EPROM writing circuit includes: a cell array 10 having a plurality of EPROM cells; a word line decoder 20 for decoding a writing signal Wpgm and an inputted address (addr[7:0]) and selecting a corresponding word line among a plurality of word lines (wl0.about.wl15); a bit line decoder 30 for decoding the writing signal Wpgm and an inputted address (Addr[7:0]) and selecting a corresponding bit line among a plurality of bit lines BL0.about.BL15; a power switch 40 switched by the writing signal Wpgm and supplying a voltage to the voltage distribution unit 50; a voltage distribution unit 50 for suitably stepping down a booster voltage by the voltage Vps outputted from the power switch 40 and outputting it; and a switching unit 60 selected by the output signal of the bit line decoder 30 and outputting the voltage stepped down by the voltage distribution unit 50 to the cell array 10.
FIG. 2 is a view of showing a detailed construction of the power switch unit 40.
The power switch unit 40 includes an inverter Inv1 for inverting the writing signal Wpgm, a PMOS transistor PM1 and an NMOS transistor NM1 and a PMOS transistor PM2 and an NMOS transistor NM2, which are constructed in parallel and connected in series between the booster voltage Vpp and the ground voltage Vss.
The voltage distribution unit 50 includes NMOS transistors NM10 and NM11 which are connected in series between the booster voltage Vpp and the first node V1. The voltage distribution unit 50 is enabled by the output voltage Vps of the power switch 40 so as to output a stepped-down voltage to the switching unit 60.
The switching unit 60 includes a plurality of NMOS transistors NM21.about.NM36, and transmits an output voltage of the voltage distribution unit 50 to the bit line of the EPROM cell through a gate selected by the writing signal Wpgm and the bit line address decoder 30.
The writing operation of the general EPROM cell in accordance with the conventional art will now be described with reference to FIGS. 1 and 2.
When the address Addr[7:0] is applied to the word line decoder 20 and the bit line decoder 30, the word line decoder 20 and the bit line decoder 30 are enabled by the writing signal Wpgm and decode the address addr [7:0] to thereby select corresponding word line and bit line among the plurality of word lines WL0.about.WL15 and the bit lines BL0.about.BL15, respectively.
Here, if a low level writing signal Wpgm is applied, the word line decode 20 and the bit line decoder 30 are disabled upon receipt of it, the power switch 40 and the NMOS transistor NM1 are turned off upon receipt of it, and the NMOS transistor NM2 and the PMOS transistor PM1 are turned on, according to which the power switch 40 outputs the ground voltage Vss.
Meanwhile, if a high level writing signal Wpgm is applied, the word line decoder 20 and the bit line decoder 30 are enabled upon receipt of it, to output word line WL0.about.WL15 signals and bit line signals BL0.about.BL15.
At this time, the NMOS transistor NM1 is turned on as the high level writing signal Wpgm is applied thereto, and at the same time, the NMOS transistor NM2 is turned off as the inverted writing signal is applied thereto, according to which the PMOS transistor PM2 is turned on so that the power switch 40 outputs the booster voltage Vpp.
Accordingly, the voltage distribution unit 50, which receives the high level signal of the power switch 40 by the commonly connected gates, steps down the booster voltage applied to the drain as the NMOS transistors NM10 and NM11 that are connected in series, and outputs it.
Upon receipt of the voltage stepped down by the voltage distribution unit 50 through the first node V1, the switching unit 60 outputs it to corresponding bit lines through the NMOS transistors NM21.about.NM36 enabled by the signal of the bit line decoder 30 among the plurality of NMOS transistors NM21.about.NM36, and applies the booster voltage Vpp to the corresponding EPROM cell of the cell array 10 enabled by the word line WL0.about.WL15 signals of the word line decoder 20, thereby performing writing operation.
Writing time in the EPROM cell is determined by the voltage level of the word line WL0.about.WL15 signals and bit line BL0.about.BL150 signals.
However, the booster voltage Vpp is applied to the corresponding word lines WL0.about.WL15 as it is and the step-own voltage, that was lowered down by the voltage distribution unit 50, is applied to the bit lines BL0.about.BL15. Consequently, when the higher voltage than or the same voltage as that of the gate is applied to the drain of the EPROM cell, since the hot electron accelerated at the source is not trapped to the floating gate of the EPROM cell but flows to the drain, writing operation is not performed. On the other hand, if the drain voltage is lower than the gate voltage, no hot electron is generated, causing that the writing time is much increased.